The 'AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed 2Q8 2D8 specifically for driving highly capacitive or 23 26
2OE 2LE relatively low-impedance loads. They are 24 25 particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AHC16373 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AHC16373 is characterized for operation from 40°C to 85°C.
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Members of the Texas Instruments Widebus(TM) Family EPIC(TM) (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-VCC VCC Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
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Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V I (see Note 1) . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, I OK (VO < 0 or VO > VCC ) . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to V CC) . . . . . . . . . . . . . 25 mA
Continuous current through each VCC or GND . . . . . . . . . . . . .. . ±75 mA
Package thermal impedance, q JA (see Note 2): DGG package . . .70°C/W
DGV package . . . 58°C/W
DL package
Post a Buying Lead
Required Field 
